A semiconductor memory device, such as a dynamic random access memory (DRAM) is typically tested at the end of the wafer processing steps. Various tests are performed. Such tests include a redundancy test for identifying defective cells and a reference potential test for checking the internally generated reference potentials. After the tests are performed, on-chip fuses may be programmed to use redundant circuits for replacing defective memory cells or for adjusting internally generated reference potentials. The on-chip fuses may be programmed by using a laser to blow selected fuses, thus selectively creating open fuses and intact (unblown) fuses.
After the fuses have been programmed, wafer testing is repeated to check whether the repaired chips properly function under different operating conditions. Functional devices are then assembled, re-tested and shipped to customers.
Depending on the system that the semiconductor device is to be used in, the signal input interface specifications (signals from an external bus onto an input pin of the semiconductor device) can differ. Two typical interface specifications are low voltage transistor-transistor logic (LVTTL) and stub series terminated logic (SSTL).
In LVTTL mode, the input signal specifications are that a high logic level (VIH) is 2.0 volts and a low logic level (VIL) is 0.8 volts. Thus, a signal that is 2.0 volts or higher is to be detected as logic high and a signal that is 0.8 volts or lower is detected as logic low. The bus frequency in LVTTL mode can be 100 MHz and the pulse width of the reference clock signal is 10 ns.
SSTL specifications require a higher degree of precision than LVTTL specifications. Thus, the reference voltage used to evaluate whether an input signal is high or low is applied externally to the chip. VIH is then defined as a potential that is 0.3 volts above the reference voltage. VIL is defined as a potential that is 0.3 volts below the reference voltage. Thus, a signal that is 0.3 volts or more above the reference potential is to be detected as logic high and a signal that is 0.3 volts or more lower than the reference potential is detected as logic low. The bus frequency in SSTL mode can be 133 MHz and the pulse width of the reference clock signal is 7.5 ns.
To facilitate manufacturing in a DRAM, a wire bonding option can be used to designate a device to be either a LVTTL interface device or a SSTL interface device. Thus, both a LVTTL interface device or a SSTL interface device can be manufactured with the same mask set, but can be selectively designated during the bonding process at the end of manufacturing. In this way, dedicated bond pads can be wired to different potentials to designate between LVTTL and SSTL interface.
Referring now to FIG. 12, a circuit schematic diagram of a conventional bond option circuit is set forth and given the general reference character 1200.
Conventional bond option circuit 1200 includes a reference potential generation circuit 101, transfer gates (G101 and G102), inverter IV101, resistors (R101 and R102), n-type insulated gate field effect transistor (IGFET) N103, and bond pads (PAD11 and PAD12). Bond pad PAD11 is connected to an input of inverter IV101 and an input of transfer gate G102. Transfer gate G102 has control inputs connected to bond pad PAD11 and the output of inverter IV101. Transfer gate G102 has an n-type IGFET N102 and a p-type IGFET P102. Reference potential generation circuit 101 has an output connected to an input of transfer gate G101. Transfer gate G101 has control inputs connected to bond pad PAD11 and the output of inverter IV101. Transfer gate G101 has an n-type IGFET N101 and a p-type IGFET P101. Outputs of transfer gates (G101 and G102) are commonly connected to provide primary reference potential VREF0. Resistor R101 has one terminal connected to primary reference potential VREF0 and another terminal connected to a drain of n-type IGFET N103. Resistor R102 has one terminal connected to the drain of n-type IGFET N103 and another terminal connected to VSS. N-type IGFET has a source connected to secondary reference potential VREF and a gate connected to receive a control signal C1.
The operation of conventional bond option circuit 1200 will now be described.
When bond pad PAD11 has a logic low (VSS) potential applied, transfer gate G101 is turned on and transfer gate G102 is turned off. In this way, primary reference potential VREF0 becomes the potential generated by reference potential generation circuit 101. If bond pad PAD11 has a logic high potential, transfer gate G101 is turned off and transfer gate G102 is turned on. In this way, primary reference potential VREF0 becomes the potential applied to bond pad PAD11.
When control signal C1 is high, secondary reference potential VREF is a potential determined by the ratio resistors (R101 and R102), which form a voltage divider circuit, and the potential of primary reference potential VREF. During this time, no external source should be applied to pad PAD12. When control signal C1 is low, secondary reference potential VREF has a potential determined by the potential of an external source applied to pad PAD12.
Referring now to FIG. 13, a conventional semiconductor memory device is set forth in a block schematic diagram and given the general reference character 1300.
Conventional semiconductor memory device includes a voltage-down circuit 102, voltage up circuit 103, memory cell array 104, redundant cells 105, sense amplifier 106, row decoder 107, address buffer 108, command-clock buffer 109, redundancy evaluation circuit 110, fuse circuit 110a, and data I/O buffer 111.
Voltage-down circuit 102 receives primary reference potential VREF0 and generates an internal voltage VINTS that is used for the memory cell array 104, redundant cells 105 and sense amplifier 106. Primary reference potential VREF0 is 2.1 Volts. Internal voltage VINTS has a lower potential than the primary reference potential.
Voltage-up circuit 103 receives primary reference potential VREF0 and generates an internal voltage VBOOT that is used for row decoder 107. Internal voltage VBOOT has a higher potential than the primary reference potential.
Address buffer 108, command-clock buffer 109, and data I/O buffer 111 receives secondary reference potential VREF. Secondary reference potential VREF is used as in input level reference in circuits that receive externally generated signals.
Address buffer 108 receives external address signals ADD and provide internal address signals to row decoder 107 and redundancy evaluation circuit 110. Redundancy evaluation circuit 110 determines whether the received internal address signals match a defective address (based on a programmed state of fuse circuit 110a). If so, the row decoder 107 is disabled and a row of redundant cells is selected from redundant cells 105. If not, the row decoder 107 is enabled and a row of memory cells is selected from memory cell array 104.
Command-clock buffer 109 receives a column address strobe signal CAS, write-enable signal WE, chip-select signal CS, and clock signal CLK. Command-clock buffer 109 provides control for read/write operations from/to memory cell array 104.
Sense amplifier 106 senses data from a selected row of memory cells and data I/O buffer 111 provides a read/write circuitry to provide data to or receive data from external data pins DQ.
Referring now to FIG. 14, a circuit diagram of an input buffer is set forth and designated by the general reference character 1400. Input buffer 1400 can correspond to input buffers that receive external signals in address buffer 108, command-clock decoder 109, or data I/O buffer 111.
Input buffer 1400 includes p-type IGFETs (P11 and P12) and n-type IGFETs (N11 and N12). N-type IGFETs N11 and N12) are input devices and p-type IGFETs (P11 and P12) are load devices. P-type IGFET P11 has a source connected to supply potential VDD, and a drain and gate connected to a drain of n-type IGFET N11. P-type IGFET P12 has a source connected to supply potential VDD, a drain connected to a drain of n-type IGFET N11, and a gate connected to the gate of p-type IGFET P11. N-type IGFET N11 has a gate connected to receive secondary reference potential VREF and a source connected to supply potential VSS. N-type IGFET N12 has a gate connected to receive an input signal IN and a source connected to supply potential VSS.
Input buffer 1400 operates as a comparator. If the potential of input signal IN is less than secondary reference potential VREF, n-type transistor N11 is turned on harder than n-type transistor N12 and output signal OUT is high. If the potential of input signal IN is higher than secondary reference potential VREF, n-type transistor N12 is turned on harder than n-type transistor N11 and output signal OUT is low. In this way input buffer 1400 acts as an inverting input buffer in that output signal OUT is inverted with respect to input signal IN. Input buffer 1400 is a differential amplifier and can detect small differences in potential between input signal IN and secondary reference potential VREF.
Referring to FIGS. 12, 13, and 14, in a conventional semiconductor device 1300 incorporating conventional bond option circuit 1200 and input buffer 1400, the device is tested at the end of the manufacturing process and before packaging. Such a wafer testing procedure is carried out by applying a potential of 2.1 volts to bond pad PAD11 of bond option circuit. With a potential of 2.1 volts applied to bond pad PAD11, pass gate G102 is turned on and pass gate G101 is turned off. The 2.1 volts applied to bond pad PAD11 provides the primary reference voltage VREF0. Control signal C1 is high and the secondary reference potential VREF becomes a potential that is proportional to primary reference voltage VREF0 based on the values of resistors (R101 and R102).
An external potential is applied for testing because the potential provided by reference potential generation circuit 101 can vary among wafers that are processed in different batches or lots. In this way, the test results can be compared with results obtained when reference potential generation circuit 101 generates primary reference voltage VREF0.
After wafer testing, the device is programmed to operate in either LVTTL mode or SSTL mode. If the device is programmed to operate in LVTTL mode, bond pad PAD11 is bonded to supply potential VSS, control signal C1 is set at a high potential and bond pad PAD12 is left to float. In this way, pass gate G102 is turned off and pass gate G101 is turned on. Reference potential generation circuit 101 provides primary reference potential VREF0. N-type IGFET N103 is turned on. Secondary reference potential VREF is proportional to primary reference potential VREF0 based on the values of resistors (R101 and R102).
If the device is programmed to operate in SSTL mode, bond pad PAD11 is bonded to supply potential VSS, control signal C1 is set at a low potential (VSS) and bond pad PAD12 is bonded to an external pin for receiving a reference potential. In this way, pass gate G102 is turned off and pass gate G101 is turned on. Reference potential generation circuit 101 provides primary reference potential VREF0. N-type IGFET N103 is turned off. Secondary reference potential VREF is equal to the externally applied reference potential receive at bond pad PAD12. The potential externally applied to bond pad PAD12 is 1.5 volts.
Referring to FIG. 14, the secondary reference potential VREF is generated internally when in the LVTTL mode and externally when in the SSTL mode. In both modes it is desirable to set the secondary reference potential at a mid-point between VIH and VIL. This will give the maximum differential potential for input buffer 1400 to detect and will allow faster circuit operation and more reliable input noise margins.
As illustrated in the conventional semiconductor memory device 1300, a separate bond pad PAD11 is needed to allow the primary and secondary reference potentials (VREF0 and VREF) to be tested. In the normal mode of operation bond pad PAD12 is used to provide secondary reference potential VREF for SSTL mode operation.
As a semiconductor memory devices get smaller, fewer bond pads are available that can be dedicated for bond options and testing. This is particularly true among devices having a wide DQ configuration as is typical among present day DRAMs.
In the conventional bond option circuit 1200 in FIG. 12, a separate bond pad may be required to provide the potential on the control gate of N-type IGFET N103 in LVTTL mode and SSTL mode devices.
Also, if the primary reference potential VREF0 supplied during the wafer test shifts, internal circuits that receive potentials based on the primary reference potential may not function correctly. Transfer gates (G101 and G102) include p-type IGFETs that may have p-n junctions forward biased when a reference potential is applied to bond pad PAD11 during testing. This can cause latch-up to occur by turning on parasitic bipolar transistors and my lead to the destruction of the device under test.
Also, when testing the secondary reference potential VREF, control signal C1 must be high. However, when switching back to a normal mode of operation, control signal C1 must become low. If the switching of control signal C1 is provided by an input buffer, then there may be problems with affecting the secondary reference potential while switching control signal C1 and this may affect the difference between an input logic value and secondary reference potential so that input buffers may incorrectly evaluate received signals.
In view of the above discussion, it would be desirable to provide a semiconductor memory device with a reduced number of bond pads while still providing an accurate method of testing reference potentials and circuit operation. It would also be desirable to test a semiconductor device having two different input interfaces that may be selected during the manufacturing phase of the device.